1. Field of the Invention
This invention relates to the formation of integrated circuit structures. More particularly this invention relates to the planarizing, by chemical-mechanical polishing, of metal-filled trenches and/or vias of integrated circuit structures.
2. Description of the Related Art
Aluminum and tungsten metals have long been used in integrated circuit structures as filler materials for vias and contact openings as well as for the construction of metal lines or interconnects. However, with ever increasing demands for faster speeds, there has been renewed interest in the use of copper as a filler material for vias and contact openings instead of tungsten, as well as for use in metal lines instead of aluminum because of the well known low electrical resistance of copper, compared to either aluminum or tungsten.
But there are negative aspects to the choice of copper for via filling or in the formation of metal lines. The usual patterning of a blanket-deposited metal layer through a mask to form a pattern of metal lines or interconnects cannot easily be carried out using copper, resulting in the need to first deposit a dielectric layer such as silicon oxide, and then form a series of trenches in the dielectric layer corresponding to the desired pattern of metal lines or interconnects. The trench surfaces are then lined with a diffusion barrier layer or liner (to prevent migration of copper into the dielectric material, as well as to promote adhesion of the filler metal to the trench surfaces), and then filled with copper metal by first forming a copper seed layer over the barrier layer, e.g., by a CVD process, and then filling the remainder of the trench with a blanket deposition of copper, e.g., by a copper plating process.
Finally, the surface portions of both the diffusion barrier layer and the copper layer, formed over the top surface of the dielectric layer during the blanket depositions, are removed using a planarization process such as a chemical-mechanical polishing (CMP), leaving the desired pattern of metal lines or interconnects in the trenches, with the copper metal in the trenches separated from the silicon oxide sidewalls of the trench by the diffusion barrier layer.
While the copper lines or interconnects formed using such procedures provide the desired increased speed of the conductor, and the presence of the diffusion barrier layer between the copper and the silicon oxide dielectric material addresses the problem of diffusion of the copper ions or atoms into the silicon oxide sidewalls, the deposition of copper metal results in a non-planar upper surface of the deposited copper layer, which surface is characterized by depressed regions over the trenches filled by the copper deposition process. Subsequent removal of the surface portions of the copper layer by chemical-mechanical polishing (CMP) can result in dishing of the copper remaining in the trench in such a way that the dishing of the copper filling drops below the upper surface of the dielectric layer which defines the trench.
Turning now to prior art FIGS. 1-3, the formation of copper interconnects or lines in a dielectric layer of an integrated circuit structure, in accordance with the prior art, will be illustrated, using the so-called dual damascene process, it being understood that the same planarizing problems are also present when using the single damascene process. As shown in FIG. 1, a dielectric layer 20 may be formed over an integrated circuit structure 10 which may comprise active devices previously formed in an underlying silicon substrate and filled vias or contact openings previously formed in an underlying dielectric layer. Such vias or contact openings provide connection, for example, with underlying gate electrodes and source/drain regions of MOS devices of integrated circuit structure 10 formed in the silicon substrate, as is well known to those skilled in the art.
Still referring to FIG. 1 formed in dielectric layer 20, are trenches 22 and 24, and vias 26 and 28. Trenches 22 and 24, and vias 26 and 28, may be formed in dielectric layer 20, for example, by twice etching dielectric layer 20 through a resist mask, to divide dielectric layer 20 into the illustrated pattern of trenches and vias in dielectric layer 20 as is well known to those skilled in the art. Trenches 22 and 24, and vias 26 and 28, represent or illustrate a series of trenches and vias generally formed in dielectric layer 20 in a pattern corresponding to a desired array of metal lines and vias to electrically interconnect, for example, underlying gate electrodes and source/drain regions of MOS devices with other portions of the integrated circuit structure.
Over the surfaces of trenches 22 and 24, vias 26 and 28, and the illustrated upper surfaces of dielectric layer 20, is formed a highly conformal diffusion barrier layer 30 comprising and electrically conductive material, for example, tantalum metal, tantalum nitride, tungsten metal, tungsten nitride, titanium metal, or titanium nitride, or combinations of same. Diffusion barrier layer 30 is blanket deposited over the surfaces of trenches 22 and 24, vias 26 and 28, and the upper surface of dielectric layer 20, by a suitable deposition process such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), or any other suitable deposition process to a thickness of, for example, from about 100 xc3x85 to about 1000 xc3x85.
Following the formation of barrier layer 30, a layer of copper metal 40 is blanket deposited over the structure by any suitable deposition process to completely fill the remaining portions of trenches 22 and 24 and vias 26 and 28, as well as depositing over the portions of barrier layer 30 previously deposited on the top surfaces of silicon oxide dielectric layer 20, as also shown in FIG. 1. This copper layer serves as the main metal conductor of trenches 22 and 24 and vias 26 and 28.
Following the blanket deposition of copper layer 40, the structure is subject to a chemical-mechanical polishing (CMP) process to remove all of the copper on the portions of diffusion barrier layer 30 on the top surfaces of dielectric layer 20, as shown in prior art FIG. 2, leaving only depressed copper portions 42 and 44 filling respective trenches 22 and 24 and vias 26 and 28. After removal of all copper from above the top surfaces of layer 20, the CMP process is continued to remove all portions of diffusion barrier layer 30 over the top surfaces of dielectric layer 20, leaving only a liner of diffusion barrier material on the walls of the trenches separating the copper metal in trenches 22 and 24 and vias 26 and 28 from the silicon oxide surfaces or walls of the trenches, as shown in prior art FIG. 3.
During the CMP planarization, copper layer 40 and barrier layer 30 are polished until the portions of copper layer 40 and barrier layer 30 lying above dielectric layer 20 are removed. Since CMP planarization is a conformal process, the depressed portions of layer 40 depicted in FIG. 1 continue to be depressed throughout the CMP process. The result, as shown in prior art FIG. 3, is a dished or depressed upper surface of the copper filler material in trenches 22 and 24, as shown, respectively, at 52-and 54 in trenches 22 and 24. Furthermore, while the problem of surface erosion of the metal trench filler material during CMP planarization has been discussed and illustrated, with respect to its occurrence with copper, the problem also exists when tungsten is used instead of copper, which includes, for example, in vias or contact openings where, tungsten is used more often as the filler material.
It would, therefore, be desirable to control the polishing of metal portions above trenches and vias in forming a pattern of metal interconnects or lines in previously formed trenches and/or vias in a layer of insulation material in order to reduce or prevent dishing of the metal surface of the filler metal in the trenches.
The invention provides a process for selectively polishing a main electrically conductive layer of an integrated; circuit structure by the steps of forming a polishing barrier layer over depressed regions of the main electrically conductive layer; and polishing the portion of the main electrically conductive layer not covered by the polishing barrier layer. The integrated circuit structure treated by the process of the invention contains one or more openings in a layer of dielectric material, and the main electrically conductive layer fills the one or more openings such that the depressed regions of the main electrically conductive layer overlie said one or more openings.